| 008 |
|
041130s2004 ch a e 001 0 chi d |
| 020 |
|
|a0471441481 ((cloth)) : |cNT$1020
|
| 040 |
|
|aTMUE|beng|cTMUE|dTMUE|eCCR
|
| 050 |
14
|
|aTK7885.7|bP37 2004
|
| 082 |
04
|
|a621.392
|
| 100 |
1
|
|aPadmanabhanT.R
|
| 245 |
10
|
|aDesign through Verilog HDL / |cT.R. Padmanabhan, B. Bala Tripura Sundari
|
| 260 |
|
|aHoboken, NJ : |bJohn Wiley : |bIEEE Press, |cc2004
|
| 300 |
|
|axii, 455 p : |bill ; |c25 cm
|
| 504 |
|
|aIncludes bibliographical references (p. 449-450) and index
|
| 700 |
1
|
|aTripura Sundari B. Bala
|
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